1. Field of the Invention
This invention relates to a package for a central-pad chip and a manufacturing method thereof, and more particularly, to an improved substrate and a method for dealing with molding flash.
2. Description of the Related Art
FIG. 1 depicts a conventional package 100 for use in packaging a central-pad chip. The package 100 comprises a semiconductor chip 110 mounted on a substrate 120. The semiconductor chip 110 has a plurality of bonding pads (not shown) centrally formed on the active surface thereof. The substrate 120 has a slot 122 corresponding to the chip connection pads of the semiconductor chip 110. The semiconductor chip 110 is securely attached to the upper surface of the substrate 120 by an adhesive layer 112. The lower surface of the substrate 120 is provided with a plurality of solder pads 124 and chip connection pads 126. Each of the solder pads 124 is connected to one end of the corresponding chip connection pad 126 through a conductive trace (not shown) formed on the substrate 120. The chip connection pads 126 of the substrate are electrically connected to the bonding pads of the semiconductor chip 110 through a plurality of bonding wires (e.g. gold wires 130). Typically, the lower surface of the substrate 120 is covered by a solder mask 128 in a manner that the solder pads 124 and the chip connection pads 126 are exposed through the solder mask. Each solder pad 124 is provided with a solder ball 140 for making external electrical connection.
Referring to FIG. 1 again, the conventional package 100 has a package body for protecting the semiconductor chip against the external moisture and/or contamination. The package body includes a first portion 150a formed on the upper surface of the substrate 120 and around the semiconductor chip 110, and a second portion 150b formed within the slot 122 of the substrate 120 for sealing the wires 130. The package body is generally formed by transfer molding.
However, when the second portion 150b of the package body is formed by the plastic molding method, the package encapsulant not only seals the slot 122 of the substrate 120 and the wires 130, but extends along the interface between the mold and the substrate to the surface of the solder mask 128 near the slot 122. The excess encapsulant hereinafter called xe2x80x9cflashxe2x80x9d, i.e. encapsulant other than that necessary to seal the slot and the wires, must be removed. However, when the excess encapsulant is peeled away from the surface of the solder mask 128, it always causes damage to the package 100. This damage can be cosmetic (e.g. marring of the substrate surface) and/or functional (e.g. tearing away of the solder mask on the substrate surface to undesirably expose the electrically conductive traces, and/or weakening or breaking of the seal between the package body and the substrate surface).
Furthermore, in mass production, it is desirable to form the package body by mold array package (MAP) molding process. However, the mold used in MAP molding process often fails to seal tightly against the substrate surface near the slot 122, and hence the flash becomes a more serious problem and even extends along the interface between the mold and the substrate to the surface of the solder pads 124 near the slot 122.
Thus, a need continues to exist in semiconductor packaging industry for improved substrates and methods, which deals with unwanted flash.
It is an object of the present invention to provide an improved substrate and a method for molding the central-pad chip, wherein the molding flash could be removed easily without damage.
To achieve the above listed and other objects, the present invention provides a substrate having opposing upper and lower surfaces and a slot defined therein. The upper surface of the substrate is adapted for receiving a semiconductor chip. The lower surface of the substrate is provided with a plurality of solder pads and a plurality of chip connection pads electrically connected to the solder pads respectively. The lower surface of the substrate is covered by a solder mask such that the solder pads and the chip connection pads are exposed through the solder mask. Preferably, both the solder pads and the chip connection pads have a layer of nickel formed on the surface thereof and a layer of gold or palladium formed on the nickel layer. The substrate is characterized by having an organic surface protection formed on the solder mask and around the slot of the substrate, wherein the chip connection pads remain uncovered by the organic surface protection. It should be understood that the organic surface protection might cover the entire surface of the solder mask and the solder pads. Preferably, the organic surface protection is made of an organic solderability preservative (OSP). Furthermore, the substrate according to the invention is one of an array of substrates formed in a strip configuration.
To achieve the above listed and other objects, the present invention further provides a method for manufacturing a semiconductor chip package utilizing the aforementioned substrate, which comprises the following steps: (a) providing a semiconductor chip having a plurality of chip connection pads centrally formed thereon; (b) mounting the semiconductor chip to the upper surface of the substrate such that the bonding pads are corresponding to the slot of the substrate; (c) wire bonding the chip connection pads of the semiconductor chip to the corresponding chip connection pads; (d) forming a package body having a first portion on the upper surface of the substrate and around the semiconductor chip, and a second portion within the slot of the substrate, wherein the molding flash is formed completely on the surface of the organic surface protection; (e) removing the organic surface protection and the molding flash thereon, and (f) forming solder balls on the solder pads after removing the organic surface protection and the molding flash. Preferably, the step of forming the package body is conducted by a mold array package (MAP) molding process.
It is noted that the molding flash is formed completely on the surface of the organic surface protection in step (d); hence, in step (e), the molding flash can be removed easily without damage. Furthermore, because the organic surface protection can cover the solder pads near the slot of the substrate, the organic surface protection can protect the solder pads from being contaminated by flash. Without the problem of the flash, the distance between the solder pads and the slot can be substantially shortened thereby improving the electrical efficiency through shortening the circuit.
This invention further provides a method for manufacturing a substrate, which comprises the following steps: (a) providing a printed circuit board having an upper surface, a lower surface and a slot defined therein, wherein the lower surface of the printed circuit board is provided with a plurality of solder pads and chip connection pads electrically connected to the solder pads respectively, and covered by a solder mask such that the solder pads and the chip connection pads are exposed through the solder mask, (b) masking the chip connection pads, e.g., by attaching a protective tape to the lower surface of the printed circuit board to cover the chip connection pads; and (c) forming an organic surface protection on the solder mask and around the slot of the substrate. Preferably, step (c) is conducted by the following steps: (1) acid cleaning and microetching the printed circuit board with the protective tape attached thereon; (2) dipping the printed circuit board into an organic solderability preservative (OSP) solution thereby forming the organic surface protection on the surface of the printed circuit board without the protection of the tape; and (3) drying the printed circuit board. Preferably, the substrate manufacturing method of the present invention further comprises a step of electroplating a layer of nickel to the solder pads and the chip connection pads on the lower surface of the substrate and the chip connection pads, and electroplating a layer of gold or palladium on the nickel layer.